It is known to provide check data in association with payload data. The payload data may, for example, be being read from a memory or transmitted over a data communication channel. Bit errors within the payload data may be detected and/or corrected using the check data. The check data may also provide the ability to detect errors within the check data itself. Such mechanisms for providing check data in association with payload data are beneficial in providing an increased resilience against bit errors.
A problem with the provision of such check data is that the necessary circuits for generating and using the check data add circuit area, cost, complexity and latency to the processing. FIG. 1 of the accompanying drawings illustrates a system in which payload data is received on a data input line 2 and supplied to a multiplexer 4 which can reorder the payload data in dependence upon an order select control signal generated by order select circuit 6. The data may require reordering as it is not supplied in the same order in which it was originally encoded, e.g. memory reads have taken place in a different order, endianess has been changed, or for some other reason. Accordingly, the multiplexer 4 reorders the payload data into the order in which it was subject to encoding when the accompanying payload check data on check data signal line 8 was generated. A decoder 10 serves to decode the reordered payload data and to compare this with the received check data to ensure that the payload data contains no bit errors and/or correct any bit errors which may be present (subject to the limitations of the check data coding). The decoder 10 may also check for bit errors within the check data itself An encoder 12 re-encodes the payload data and generates new check data for output on check data signal line 14.
In the serial approach illustrated in FIG. 1, the critical path of the processing has two major components. Firstly, the order select circuit 6 needs to control the data reordering by the multiplexer 4 before the decoder 10 can commence operation. Secondly, the check data output on check data output line 14 is generated in dependence upon the corrected payload data which is produced by the decoder 10. Both of these aspects disadvantageously increase the latency associated with the processing of the circuitry of FIG. 1.